Depends entirely on what banking scheme you use. Nothing stops you from adding e.g. an 8-bit banking register (even two of them, one for instruction fetches, another one for normal memory reads/writes) to serve as bits 23–16 for the 24-bit memory bus. That's what WDC 65C816 from 1985 does, but it also goes full 16-bit mode as well.
And if you have a 16-bit CPU, you can do all kinds of silly stuff; for instance, you can have 4 16-bit MSRs, let's call them BANK0–BANK3, that would be selected by the two upper bits of a 16-bit address, and would provide top 16 bits for the bus, while the lower 14-bits would come from the original address. That already gives you 30 bits for 1 GiB of addressable physical memory (and having 4 banks available at the same time instead of just 2 is way more comfortable) and nothing stops you from adding yet another 4 16-bit registers BANK0_TOP–BANK3_TOP, to serve as even higher 16 bits of the total address — that'd give you 16+16+14 = 46 bit of physical address (64 TiB) which is only slightly less than what x64 used to give you for many years (48 bits, 256 TiB).
> Even 4MB would take you hours to load from floppies with a 6502.
Depends on your clock. Also, you could use some dedicated hardware, like a DMA controller e.g. 8257, or 8237. From 8257's datasheet:
Speed
The 8257 uses four clock cycles to transfer byte of
data. No cycles are lost in the master to master transfer
maximizing bus efficiency. 2MHz clock input will
allow the 8257 to transfer at rate of 500K bytes/second.
and I recall 8237 could do even better, if wired and programmed properly.
Hard drivers were available for the 6502. They were expensive ($10k for a 10MB drive as I recall prices came down a lot, but never affordable in the 1980s)
Processing terabytes with a single CPU was impractical, but you could in theory connect it.
And if you have a 16-bit CPU, you can do all kinds of silly stuff; for instance, you can have 4 16-bit MSRs, let's call them BANK0–BANK3, that would be selected by the two upper bits of a 16-bit address, and would provide top 16 bits for the bus, while the lower 14-bits would come from the original address. That already gives you 30 bits for 1 GiB of addressable physical memory (and having 4 banks available at the same time instead of just 2 is way more comfortable) and nothing stops you from adding yet another 4 16-bit registers BANK0_TOP–BANK3_TOP, to serve as even higher 16 bits of the total address — that'd give you 16+16+14 = 46 bit of physical address (64 TiB) which is only slightly less than what x64 used to give you for many years (48 bits, 256 TiB).